DocumentCode

2575587

Title

Fpga Synthesis With Retiming And Pipelining For Clock Period Minimization Of Sequential Circuits

Author

Cong, Jason ; Wu, Chang

Author_Institution

Department of Computer Science University of California, Los Angeles, CA 90095

fYear

1997

fDate

9-13 June 1997

Firstpage

644

Lastpage

649

Keywords

Circuit synthesis; Clocks; Delay; Field programmable gate arrays; Logic; Minimization; Permission; Pipeline processing; Sequential circuits; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the 34th

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-7803-4093-0

Type

conf

DOI

10.1109/DAC.1997.597224

Filename

597224