Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

Author

Balatsoukas-Stimming, Alexios ; Raymond, Alexandre J. ; Gross, Warren J. ; Burg, Andreas

Author_Institution

Telecommun. Circuits Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland

Volume

61

Issue

8

fYear

2014

fDate

Aug. 2014

Firstpage

609

Lastpage

613

Abstract

This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a block length of N=1024 bits and list sizes L=2, 4 using a UMC 90 nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mb/s at a frequency of 459 MHz.

Keywords

VLSI; block codes; decoding; error correction codes; linear codes; UMC 90 nm VLSI technology; bit rate 181 Mbit/s; block length; frequency 459 MHz; hardware architecture; list SC decoding; list sizes; list successive cancellation decoding; polar codes; Circuits and systems; Computer architecture; Decoding; Hardware; Indexes; Measurement; Quantization (signal); List successive cancellation (SC) decoding; polar codes; very-large-scale integration (VLSI);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2014.2327336

Filename

6823099