An Efficient and Flexible Embedded Memory IP Compiler

The efficiency and flexibility of current state-of-the-art memory compilers are often limited due to the heavy dependence on specific circuit structure, which leads to the high recurring design cost and long design cycle. To address these issues systematically, a set of novel design schemes have been proposed in this paper, including a general, scalable memory architecture that is suitable for various memories, an highly efficient layout tiling method based on overlap-distance, an automatic and easy-to-use template expansion scheme using an ASP-style tag language, and a general and accurate timing and power prediction technique based on a piecewise polynomial interpolation algorithm. To verify the effectiveness of these schemes proposed in this paper, a single-port SRAM compiler with the maximum capacity of 1Mb has been developed and taped out successfully in SMIC 65nm process.