Functional verification of the IBM zSeries eServer z900 system

Author

Walter, Joerg

Author_Institution

IBM Entwicklung GmbH, Boeblingen, Germany

fYear

2002

fDate

2002

Firstpage

17

Lastpage

21

Abstract

This paper presents an overview on how the zSeries eServer z900 system has been functionally verified. It describes the hierarchical structure of verification, starting with designer simulation, unit-simulation, chip-simulation up to system simulation. For each step, the tools, methods and goals of verification are described. It also presents a description of the IT environment used at the different levels of verification, especially of dedicated simulation hardware like accelerator and emulator machines used for system simulation and hardware/software co-verification.

Keywords

IBM computers; circuit simulation; computer testing; hardware-software codesign; network servers; IBM zSeries eServer z900 system; accelerator; chip-simulation; designer simulation; emulator machines; functional verification; hardware/software coverification; hierarchical structure; unit-simulation; Computational modeling; Computer simulation; Design engineering; Explosions; Logic design; Signal design; State-space methods; Stress; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on

ISSN

1063-6404

Print_ISBN

0-7695-1700-5

Type

conf

DOI

10.1109/ICCD.2002.1106741

Filename

1106741