POPS: A tool for delay/power performance optimization

Author

Azemard, N. ; Aline, M. ; Auvergne, D.

Author_Institution

Lab. d´´Inf., de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

2000

fDate

2000

Firstpage

276

Lastpage

280

Abstract

Based on an incremental path search algorithm, this paper addresses the problem of performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from industrial tools on examples of path enumeration and optimization evaluated on several ISCAS´85 benchmarks

Keywords

circuit CAD; circuit layout CAD; circuit optimisation; combinational circuits; delay estimation; high level synthesis; integrated logic circuits; POPS; circuit path sizing; delay performance optimization; gate delay; gate power; incremental path search algorithm; logic circuit design; performance driven path classification; performance optimization by path selection; power performance optimization; power/area constraints; Capacitance; Circuits; Delay effects; Delay estimation; Electronic mail; Energy management; Optimization; Performance analysis; Robots; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6598-4

Type

conf

DOI

10.1109/ASIC.2000.880715

Filename

880715