DocumentCode
25827
Title
Impact of Charge Trapping Layer Thickness and New Trade-Off in Performance Characteristics of 3-D SONOS Devices
Author
Arreghini, A. ; Kar, Gouri Sankar ; Van den bosch, G. ; Van Houdt, J.
Author_Institution
Imec, Leuven, Belgium
Volume
34
Issue
5
fYear
2013
fDate
May-13
Firstpage
632
Lastpage
634
Abstract
We evaluate the impact of silicon nitride (SiN) layer thickness in BiCS-like 3-D SONOS devices via standard and advanced characterization techniques, based on program (erase) efficiency measurements. SiN thickness below 4 nm strongly impacts electron trapping efficiency, resulting in degraded program operation but enhanced erase saturation level and hence giving rise to a new program-erase trade-off. An optimal 4 nm SiN thickness is assessed for proper MLC operation.
Keywords
silicon compounds; storage management chips; 3D SONOS devices; BiCS; MLC operation; SiN; charge trapping layer thickness; silicon nitride; 3-D SONOS; erase efficiency; oxide-nitride-oxide (ONO) optimization; program efficiency; program-erase trade-off; silicon nitride (SiN) thickness;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2013.2253442
Filename
6504469
Link To Document