Title :
Formal representation of gated clock designs
Author :
Seceleanu, Tiberiu ; Plosila, Juha
Author_Institution :
Turku Centre for Comput. Sci., Turku, Finland
Abstract :
The action systems formal framework has recently been applied to the area of asynchronous and synchronous VLSI design. In this paper, we present aspects of formal gated clock design. This proves useful when targeting mixed-architecture designs: devices composed of subsystems that operate in an asynchronous manner with respect to each other, even though some of them may have synchronous implementations. The modeling of gated clock systems is built on top of the synchronous operators
Keywords :
VLSI; asynchronous circuits; clocks; formal specification; integrated circuit design; logic CAD; low-power electronics; asynchronous VLSI design; formal representation; gated clock designs; mixed-architecture designs; synchronous VLSI design; synchronous operators; Clocks; Computer science; Consumer electronics; Costs; Digital circuits; Energy consumption; Physics; Power system modeling; Transformers; Very large scale integration;
Conference_Titel :
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6598-4
DOI :
10.1109/ASIC.2000.880763
