Simultaneous state, Vt and Tox assignment for total standby power minimization

Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (I_gate) has become comparable to subthreshold leakage (I_sub) in 90 nm technologies. In this paper, we propose a new method that uses a combined approach of sleep-state, threshold voltage (V_t and gate oxide thickness (T_ox) assignments in a dual-V_t and dual-T_ox process to minimize both I_sub and I_gate. Using this method, total leakage current can be dramatically reduced since in a known state in standby mode, only certain transistors are responsible for leakage current and need to be considered for high-V_t or thick-T_ox assignment. We formulate the optimization problem for simultaneous state, V_t and T_ox assignments under delay constraints and propose two practical heuristics. We implemented and tested the proposed methods on a set of synthesized benchmark circuits. Results show an average leakage current reduction of 5a-6X and 2-3X compared to previous approaches that only use state or state+V_t assignment, respectively, with small delay penalties.