Title :
A fast algorithm for critical path tracing in VLSI digital circuits
Author :
Wu, Lei ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets.
Keywords :
digital integrated circuits; integrated circuit testing; very high speed integrated circuits; VLSI digital circuits; linear path critical path tracing; stem analysis; stem criticality; Circuit faults; Circuit simulation; Computational modeling; Digital circuits; Fault detection; Fault diagnosis; Logic; Observability; Testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on
Print_ISBN :
0-7695-2464-8
DOI :
10.1109/DFTVS.2005.6
