DocumentCode
258454
Title
A conceptual toolchain for an application domain specific reconfigurable logic architecture
Author
Bostelmann, Timm ; Sawitzki, Sergei
Author_Institution
Fachhochschule Wedel, Univ. of Appl. Sci., Wedel, Germany
fYear
2014
fDate
8-10 Dec. 2014
Firstpage
1
Lastpage
4
Abstract
In this paper we present a concept of a reconfigurable logic toolchain. The specialty of this toolchain is the highly configurable architecture design. The goal is to provide the designer with the ability to suit the architecture of the reconfigurable logic to a specific application domain, for example communication or image processing. Thereby the disadvantages of very flexible, universal structures like FPGAs (inefficient resource usage and high communication overhead) can be diminished. At the same time their advantages (short time to market and low non-recurring engineering costs) can be kept. To achieve this a graphical architecture editor allows the user to adapt the global design structure as well as the detailed implementation of the logic cells. An analysis tool reports how frequently the different logic and routing resources of the described architecture are utilized by a given set of applications, to allow an optimization towards a specific application domain. We show the degrees of freedom the envisioned toolchain offers and discuss the corresponding trade-offs. Furthermore we show which steps of the development toolchain have to be adapted to the needs of such a flexible architecture and how this can be done. Finally we present the status of this work in progress and give a prospect to the planned future work.
Keywords
application specific integrated circuits; circuit optimisation; electronic design automation; field programmable gate arrays; logic CAD; logic design; reconfigurable architectures; time to market; FPGA; analysis tool; application domain specific reconfigurable logic architecture; communication overhead; conceptual toolchain; development toolchain; flexible architecture; global design structure; graphical architecture editor; highly configurable architecture design; image processing; logic cells; nonrecurring engineering cost; optimization; reconfigurable logic toolchain; resource usage; specific application domain; time to market; Digital signal processing; Field programmable gate arrays; Logic gates; Optimization; Routing; Switches; Video recording;
fLanguage
English
Publisher
ieee
Conference_Titel
ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on
Conference_Location
Cancun
Print_ISBN
978-1-4799-5943-3
Type
conf
DOI
10.1109/ReConFig.2014.7032487
Filename
7032487
Link To Document