An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed

In this paper, we introduce an IP-core which operates as glue logic between the programmable logic of a FPGA and a Cypress EZ-USB FX3 (FX3) USB-3.0 transceiver. The developed IP core communicates with other logic via AXI-4 and enables half duplex connections between the linked logic and the FX3. Thereby the platform can be used by several applications which need a high speed communication to a USB-3.0 capable host. We chose an Enclustra Mercury KX1 board for implementation, which provides the FX3 USB-3.0 transceiver chip, a Xilinx Kintex-7 FPGA and 1 GB of DDR3 SDRAM. As an application we present a radar system. The stream of radar data is received inside the Kintex-7 by a Xilinx JESD204 IP-core and buffered in the DDR3 SDRAM. For processing, the buffered data is transmitted to a host computer via the introduced IP-core. This paper shows our implementation approach, achieved transmission rates, as well as other IP-core features and gives an outlook on future advancements and applications.