• DocumentCode
    258570
  • Title

    On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization

  • Author

    Adhinarayanan, Vignesh ; Koehn, Thaddeus ; Kepa, Krzysztof ; Wu-Chun Feng ; Athanas, Peter

  • Author_Institution
    Dept. of Comput. Sci., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • fYear
    2014
  • fDate
    8-10 Dec. 2014
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    Wideband channelization is an important and computationally demanding task in the front-end subsystem of several software-defined radios (SDRs). The hardware that supports this task should provide high performance, consume low power, and allow flexible implementations. Several classes of devices have been explored in the past, with the FPGA proving to be the most popular as it reasonably satisfies all three requirements. However, the growing presence of low-power mobile GPUs holds much promise with improved flexibility for instant adaptation to different standards. Thus, in this paper, we present optimized polyphase channelizations for the FPGA and GPU, respectively, that must consider power and accuracy requirements in the context of a military application. The performance in mega-samples per second (MSPS) and energy efficiency in MSPS/watt are compared between the two classes of hardware platforms: FPGA and GPU. The results show that by exploiting the flexible datapath width of FPGAs, FPGA implementations generally deliver an order-of-magnitude better performance and energy efficiency over fixed-width GPU architectures.
  • Keywords
    energy conservation; field programmable gate arrays; graphics processing units; low-power electronics; software radio; FPGA; MSPS/watt; SDR; energy efficiency; fixed-width GPU architecture; flexible datapath width; front-end subsystem; hardware platform; low-power mobile GPU; mega-samples per second; optimized polyphase channelization; software-defined radio; wideband channelization; Clocks; Field programmable gate arrays; Finite impulse response filters; Graphics processing units; Hardware; Memory management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on
  • Conference_Location
    Cancun
  • Print_ISBN
    978-1-4799-5943-3
  • Type

    conf

  • DOI
    10.1109/ReConFig.2014.7032542
  • Filename
    7032542