A device-agnostic tool for precomputing legal placements in modular design flows

Recent research aiming to improve FPGA productivity has focused on modular design flows where modules can be compiled into a library of blocks that can be used to rapidly assemble designs. Rapid assembly is possible because compute intensive tasks, such as detailed local placement, are handled at module compile time. This paper presents a tool known as a preplacer that computes and stores all possible legal placements of a module at module compile time. The tool presented here distinguishes itself from previous efforts to solve the same problem by leveraging the open-source TORC device databases to support all modern Xilinx devices without manually extracting the RPM grid. Legal placements are calculated efficiently by first compressing the FPGA tile layout and then using a multi-step approach to eliminate illegal placements. The preplacer run-time is insignificant within the scope of module compilation times and quality of results are comparable to the previous architecture specific implementation.