A highly efficient reconfigurable architecture of inverse transform for multiple video standards

This paper presents a flexible and reconfigurable inverse transform architecture supporting combined MPEG-2, H.264 and HEVC video decoding standards. The proposed architecture uses an 8-point parallel and pipelined process for the implementation of 1-D IDCT/IDST algorithms, supports processing of flexible image block sizes including 2×2, 4×4, 8×8, 16×16 and 32×32. This design has been captured using HDL and synthesised using Xilinx Virtex-7 FPGA technology. Results show that the combined architecture can support the IDCT/IDST of MPEG-2, H.264 and HEVC with approximately a 57% reduction in area compared to the combined area of separate coder designs.