The FPGA implementation of an image registration algorithm using binary images

The FPGA implementation of image registration algorithms is a challenging problem due to the limited resources of the hardware and the requirement for real-time processing speeds. Image registration approaches using low bit-resolution images are more feasible for implementation on FPGAs than those using full resolution images because of the significant reduction in hardware resources required. The real-time processing requirement can also be satisfied with the use of simple logic operations such as AND, XOR and NOT instead of more complex computations such as additions and multiplications. This paper presents the implementation of an image registration algorithm on two FPGAs from the SPARTAN-3E family for the case of translational motion.