Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores

Hardware Trojan horses (HTHs) are malicious inclusions or alterations to hardware designs developed and supplied by untrusted parties. The emerging threat of HTHs has a direct impact on the FPGA design community which mainly relies on third-party IP (3PIP) cores and design reuse practices. Efficient design and detection of HTHs have been the main interest of most related research work, but countermeasures against HTHs have not attained sufficient attention. We advance a novel approach promoting Smart Employment of Circuit Redundancy to Effectively Counter Trojans (SECRET) in 3PIP cores employed in reconfigurable hardware designs. Two identical instances of the protected IP core are employed for observation and operating purposes and a time shift is created between the two core inputs. Trojan detection circuitry is inserted during the design-time to monitor the observation core at run-time. Once a Trojan is detected in the observation core, the operating core with the delayed input is suspended or the identified triggering inputs are isolated for a specific period of time to bypass the Trojan activating trigger. We present the SECRET high-level architecture, a proof-of-concept application to a 3PIP crypto core containing an HTH of our design. The prototype is designed and validated on a Spartan-3 FPGA. Simulation and implementation results show the SECRET feasibility and effectiveness.