DocumentCode :
2586297
Title :
Enabling Reconfigurable Hardware Accelerators for the Grid
Author :
Dydel, Stefan ; Benedyczak, Krzysztof ; Bala, Piotr
Author_Institution :
Fac. of Math. & Comput. Sci., Nicolaus Copernicus Univ., Torun
fYear :
2006
fDate :
13-17 Sept. 2006
Firstpage :
145
Lastpage :
152
Abstract :
In this paper we describe developed hardware/software composition enabling field programmable logic devices (FPGAs) in the UNICORE grid environment. A Smith-Waterman algorithm for aminoacid and DNA sequences is implemented in FPGA PCI extension card, interfaced with Linux workstation running kernel 2.6 series through special low level module and is exposed to the final user with the UNICORE middleware. This approach gives remote, secure, uniform and easy to use graphical access to the very specialised hardware accelerated service. Additionally, great flexibility to the UNIX system is provided due to separation of a different hardware and software levels using UNICORE plugins. The approach is very effective in a BioGrid context, where we are interested in integration of sophisticate accelerated distributed computational resources and providing general grid functionality consisting of single login, job submission and control mechanism to the life sciences community
Keywords :
DNA; Linux; biology computing; field programmable gate arrays; graphical user interfaces; grid computing; middleware; operating system kernels; peripheral interfaces; reconfigurable architectures; BioGrid context; DNA sequences; FPGA PCI extension card; Linux workstation; Smith-Waterman algorithm; UNICORE grid environment; UNICORE middleware; UNIX system; aminoacid sequences; distributed computational resource; field programmable logic device; grid computing; hardware/software composition; kernel 2.6 series; reconfigurable hardware accelerator; Acceleration; DNA; Field programmable gate arrays; Hardware; Kernel; Linux; Middleware; Programmable logic devices; Sequences; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on
Conference_Location :
Bialystok
Print_ISBN :
0-7695-2554-7
Type :
conf
DOI :
10.1109/PARELEC.2006.34
Filename :
1698652
Link To Document :
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