Title :
Optimized generation of data-path from C codes for FPGAs
Author :
Guo, Zhi ; Buyukkurt, Betul ; Najjar, Walid ; Vissers, Kees
Author_Institution :
California Univ., Riverside, CA, USA
Abstract :
FPGAs, as computing devices, offer significant speedup over microprocessors. Furthermore, their configurability offers an advantage over traditional ASICs. However, they do not yet enjoy high-level language programmability, as microprocessors do. This has become the main obstacle for their wider acceptance by application designers. ROCCC is a compiler designed to generate circuits from C source code to execute on FPGAs, more specifically on CSoCs. It generates RTL level HDLs from frequently executing kernels in an application. In this paper, we describe the ROCCC´s system overview and focus on its data path generation. We compare the performance of ROCCC-generated VHDL code with that of Xilinx IPs. The synthesis result shows that the ROCCC-generated circuit takes around 2×∼3× the area and runs at a comparable clock rate.
Keywords :
C language; circuit optimisation; field programmable gate arrays; hardware description languages; hardware-software codesign; high level synthesis; program compilers; reconfigurable architectures; system-on-chip; C source code compiler; CSoC; FPGA; ROCCC; RTL level HDL; VHDL code; configurable system-on-a-chip; data-path generation optimization; frequently executing kernels; high-level language programmability; Clocks; Electronic design automation and methodology; Field programmable gate arrays; Hardware; High level languages; Integrated circuit synthesis; Kernel; Microprocessors; Optimizing compilers; Parallel processing;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.234