A new balancing technique with power losses minimization in diode-clamped multilevel converters

A new PWM technique, capable of achieving a correct dc-link capacitor voltages balance in Diode- Clamped Multilevel inverters, within the limits defined by the theory, is presented. This result is obtained while decreasing the switching power losses when compared to techniques based on the use of redundant switching vectors. The combined use of such a technique and of additional chopper stages permits the correct operation of the converter in all operating conditions, maximizing the energy efficiency and decreasing the cost of the additional passive and active components. A detailed explanation of the new devised PWM technique and the main results, including the evaluation of the converter efficiency in the most significant operating points, are reported.