DocumentCode :
2588670
Title :
A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design
Author :
Menichelli, F. ; Olivieri, M. ; Benini, L. ; Donno, M. ; Bisdounis, L.
Author_Institution :
DIE, Rome Univ., Italy
Volume :
3
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
312
Abstract :
We present the design exploration of a system-on-chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results.
Keywords :
ad hoc networks; integrated circuit design; multiprocessing systems; system-on-chip; CPU; DMA unit; HIPERLAN/2 communication protocol; ad-hoc C++ simulation environment; central processing unit; direct memory access; multiprocessor system-on-chip design; power model integration; simulation based power aware architecture; software mapping; Access protocols; Baseband; Communication standards; Computer architecture; Energy consumption; Microprocessors; Multiprocessing systems; Power system modeling; Software design; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1269256
Filename :
1269256
Link To Document :
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