A low-dropout regulator with power supply rejection improvement by bandwidth-zero tracking

Author

Yan Lu ; Ruo He Yao ; Da Qiang Huang ; Su, Julien ; Junmin Jiang ; Wing-Hung Ki

Author_Institution

Sch. of Electron. & Inf. Eng., South China Univ. of Technol., Guangzhou, China

fYear

2014

fDate

17-20 Nov. 2014

Firstpage

105

Lastpage

108

Abstract

This paper presents a low-dropout regulator (LDO) with low quiescent current, small area, and power supply rejection (PSR) improvement, implemented in 0.35μm CMOS process. A zero that tracks the unity gain frequency is employed in the feedback loop using a 1pF compensation capacitor. An improved intermediate stage is designed to split the low frequency pole and drive the power MOSFET. With no equivalent series resistor (ESR) zero requirement, the minimum DC gain and phase margin are 76dB and 70°, respectively. The proposed LDO dissipates 20μA at no-load condition and 385μA at full-load condition. The effective die area is 180×75μm² that is comparable to the size of a standard I/O. Thus, integrating the proposed LDO in system is flexible.

Keywords

CMOS integrated circuits; capacitors; compensation; low-power electronics; power MOSFET; voltage regulators; CMOS process; LDO; PSR improvement; bandwidth-zero tracking; capacitance 1 pF; compensation capacitor; current 20 muA; current 385 muA; feedback loop; low frequency pole; low quiescent current; low-dropout regulator; power MOSFET; power supply rejection improvement; size 0.35 mum; unity gain frequency; Capacitors; MOSFET; Power supplies; Regulators; Resistance; Transient response;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on

Conference_Location

Ishigaki

Type

conf

DOI

10.1109/APCCAS.2014.7032730

Filename

7032730