Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Author

Monteiro, Cancio ; Takahashi, Yasuhiro ; Sekine, Toshikazu

Author_Institution

Grad. Sch. of Eng., Gifu Univ., Gifu, Japan

fYear

2014

fDate

17-20 Nov. 2014

Firstpage

121

Lastpage

124

Abstract

This paper investigates the effectiveness of secure dual-rail adiabatic logic against power analysis attack under CMOS process variations. The ability of the previously proposed logic in multiplier over GF(2⁴) is investigated in terms of transitional energy dissipation using 100 data samples from Monte Carlo simulation. The adiabatic multiplier circuits are simulated using 0.18-μm and 90-nm CMOS process at an operating power clock frequency of 12.5MHz. The SPICE simulation results show that the proposed CSSAL multiplier has high stability and strong immunity in consuming constant power than other investigated logic styles.

Keywords

CMOS logic circuits; Monte Carlo methods; SPICE; clocks; power consumption; CMOS process variation; GF; Monte Carlo simulation; SPICE simulation; adiabatic multiplier circuits; constant power consumption; dual-rail CSSAL effectiveness; dual-rail charge-sharing symmetric adiabatic logic style; frequency 12.5 MHz; operating power clock frequency; power analysis attack; size 0.18 mum; size 90 nm; transitional energy dissipation; CMOS integrated circuits; CMOS process; Circuit stability; Cryptography; Energy dissipation; Semiconductor device modeling; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on

Conference_Location

Ishigaki

Type

conf

DOI

10.1109/APCCAS.2014.7032734

Filename

7032734