Title :
Highly scalable and CMOS-compatible STTM cell technology
Author :
Ahn, S.J. ; Koh, G.H. ; Kwon, K.W. ; Baik, S.J. ; Jung, G.T. ; Hwang, Y.N. ; Jeong, H.S. ; Kinam Kim
Author_Institution :
Adv. Technol. Dev., Samsung Electron. Co.Ltd., Kyunggi-Do, South Korea
Abstract :
The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.
Keywords :
CMOS memory circuits; 0.24 micron; CMOS-compatible STTM cell technology; I/O transistor co-process; highly scalable memory cell technology; memory array formation; scalable two transistor memory; surrounded gate STTM structure; Boron; CMOS technology; Electrons; Flash memory; Random access memory; Research and development; Testing; Threshold voltage; Transistors; Writing;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269275
