A novel W/WNx/dual-gate CMOS technology for future high-speed DRAM having enhanced retention time and reliability

Author

Saino, K. ; Kato, Y. ; Kitamura, E. ; Takaishi, Y. ; Ando, M. ; Taguwa, T. ; Kanda, T. ; Yamada, S. ; Sekiguchi, T.

Author_Institution

Technol. & Dev. Office, Elpida Memory, Inc., Kanagawa, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

This work describes a new DRAM cell technology, W/WNx/P/sup +/-gate NMOS memory cell (MC) transistors, which has been integrated into a dual-gate CMOS process. Operation speed, data retention time (t/sub REF/), and reliability of high speed DRAMs are dramatically improved by the P/sup +/-gate NMOS cell, having a low-resistance polymetal word line (WL). Transistor performance in the periphery circuit is enhanced by dual-gate CMOSFETs formed with a low temperature process. These technologies offer excellent scalability and fully operating DDR-II SDRAM test chips have been obtained.

Keywords

CMOS memory circuits; DRAM chips; MOSFET; integrated circuit reliability; tungsten; tungsten compounds; 512 Mbit; DDR-II SDRAM; P/sup +/-gate NMOS memory cell transistors; W-WN; W/WNx/dual-gate CMOS technology; data retention time; dual-gate CMOSFET; high-speed DRAM; low temperature process; low-resistance polymetal word line; operation speed; reliability enhancement; retention time enhancement; scalability; CMOS process; CMOS technology; CMOSFET circuits; Circuit testing; Integrated circuit reliability; MOS devices; Random access memory; SDRAM; Scalability; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269311

Filename

1269311