Title :
Fully compatible integration of high density embedded DRAM with 65nm CMOS technology (CMOS5)
Author :
Matsubara, Y. ; Habu, M. ; Matsuda, S. ; Honda, K. ; Morifuji, E. ; Yoshida, T. ; Kokubun, K. ; Yasumoto, K. ; Sakurai, T. ; Suzuki, T. ; Yoshikawa, J. ; Takahashi, E. ; Hiyama, K. ; Kanda, M. ; Ishizuka, R. ; Moriuchi, M. ; Koga, H. ; Fukuzaki, Y. ; Sogo
Author_Institution :
Syst. LSI Div., Toshiba Corp., Yokohama, Japan
Abstract :
65 nm node SoC technology has been achieved to show good yield of 8 Mbit DRAM ADM using tapered BF/sub 2/ implantation without an additional mask step, the cell size of which is 0.11 /spl mu/m/sup 2/, with 3 layers of hybrid low-k material, SiLK/BD/BLOk, and Cu integration.
Keywords :
CMOS memory circuits; DRAM chips; boron compounds; copper alloys; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; system-on-chip; 65 nm; 8 Mbit; ADM; BF/sub 2/; CMOS5 technology; Cu; Cu dual-damascene interconnects; SiLK/BD/BLOk; SoC; embedded DRAM CMOS integration; high density DRAM yield; hybrid low-k material layers; tapered BF/sub 2/ implantation; Boron; CMOS technology; Capacitors; Degradation; Dielectric materials; Inorganic materials; Logic devices; MOSFET circuits; Random access memory; Silicides;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269313
