VLSI implementation of an edge detector based on Sobel operator

We present the design and implementation of the Sobel operator in an application specific integrated circuit. Systolic processor arrays were employed for an efficient exploitation of the advantages of VLSI technology. The architecture obtained is highly regular and simple. The performance of the architecture is improved by means of the use of carry save arithmetic. The chip was implemented using 1 μm CMOS technology and the final area is 10 mm². The resulting chip provides the values for the pixels of the gradient images (rows and columns) alternatively each clock cycle with a 20 cycle latency. The maximum operating frequency is 50 MHz and, consequently, it is an adequate design for real time image processing