DocumentCode :
2590021
Title :
An accuracy-driven complex arithmetic unit
Author :
Spaanenburg, L. ; van Drunen, R. ; Pops, A. ; Postma, A.C.W. ; Sytsma, R.
Author_Institution :
Dept. of Comput. Sci., Rijksuniv. Groningen, Netherlands
fYear :
1994
fDate :
5-8 Sep 1994
Firstpage :
491
Lastpage :
498
Abstract :
An arithmetic technique is described that allows one to speed up computation of complex operations with 30-70% by adapting the relative precision of the values. Within typical applications a characteristic improvement of upto 60% is retained. A single pipelined 32-bits arithmetic unit is defined, that supports the autonomous handling of accuracy settings while providing a direct hardware implementation for addition/subtraction, multiplication/division, power/root and a number of mixed operations such as sum of squares. In a 0.8 μm CMOS technology, this module houses 30 K transistors on a 2.5 mm2 area and operates at about 100 MHz external clock
Keywords :
CMOS digital integrated circuits; adders; dividing circuits; multiplying circuits; pipeline arithmetic; transistors; 0.8 mum; 100 MHz; 2.5 mm; 32 bit; CMOS technology; accuracy settings; accuracy-driven complex arithmetic unit; addition; autonomous handling; complex operations; computation; direct hardware implementation; division; external clock; mixed operations; module; multiplication; power; relative precision; root; single pipelined 32-bits arithmetic unit; subtraction; sum of squares; transistors; Architecture; Arithmetic; CMOS technology; Clocks; Costs; Data processing; Digital signal processing; Hardware; Packaging; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference.
Conference_Location :
Liverpool
Print_ISBN :
0-8186-6430-4
Type :
conf
DOI :
10.1109/EURMIC.1994.390366
Filename :
390366
Link To Document :
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