• DocumentCode
    259028
  • Title

    Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor

  • Author

    Kumaki, Takeshi ; Fujino, Takeshi ; Koide, Tetsushi

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan
  • fYear
    2014
  • fDate
    17-20 Nov. 2014
  • Firstpage
    359
  • Lastpage
    362
  • Abstract
    This paper presents an interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. Recent mobile devices need to apply private-information secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the product´s required-specifications, especially cipher implementation for fast processing, low power consumption, low hardware cost and adaptability. To satisfy these security-related needs, the interleaved-bitslice method for a massive-parallel SIMD matrix is proposed for parallel block cipher processing with five confidentiality modes on mobile machineries. For the AES algorithm, this processor implementation has up to 93% fewer clock cycles per byte than the conventional mobile processor. Additionally, the MX-1 results are almost constant for all confidentiality modes. Consequently, the interleaved-bitslice block cipher processing with five confidentiality modes on the MX-1 is very effective for implementation of parallel block cipher processing for several mobile devices.
  • Keywords
    cryptography; data privacy; matrix algebra; mobile computing; parallel processing; MX-1; cipher implementation; confidentiality modes; interleaved-bitslice AES decryption; interleaved-bitslice AES encryption; interleaved-bitslice block cipher processing; massive-parallel SIMD matrix; massive-parallel mobile embedded processor; mobile devices; mobile machineries; parallel block cipher processing; personal information leakage; private-information secure technology; product required-specifications; Ciphers; Clocks; Computer architecture; Encryption; Mobile communication; Parallel processing; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
  • Conference_Location
    Ishigaki
  • Type

    conf

  • DOI
    10.1109/APCCAS.2014.7032794
  • Filename
    7032794