Jitter compensation technique for continuous-time sigma-delta modulator

This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-ΣΔ modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.