Area-efficient check node unit architecture for single block-row quasi-cyclic LDPC codes

Single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are recently proposed. This kind of codes are favorable in applications because of their construction flexibility and good performance compared to PEG codes and array codes. However, the corresponding high row weight will increase the hardware complexity of the check node unit (CNU). In this paper, an area-efficient CNU architecture for single block-row QC-LDPC codes is proposed by refining the searching method for the 2^nd minimum. Implementation results of the rate-0.9333 (2115, 1974) code have shown that compared with existing design approaches, the proposed method can achieve at least 15.2% hardware reduction while keeps the latency as the same.