DocumentCode
2590696
Title
An exercise in formally based circuit synthesis from a behavioural specification in interval temporal logic
Author
Elliott, R.
Author_Institution
Sch. of Inf. Syst., East Anglia Univ., Norwich, UK
fYear
1994
fDate
5-8 Sep 1994
Firstpage
92
Lastpage
99
Abstract
Interval Temporal Logic (ITL) has been proposed as a vehicle for high level behavioural specification of digital circuits. This paper considers, by means of an example, how a circuit definition might be synthesised based on detailed analysis of a specification expressed in ITL, and compares the result with that generated by an automated synthesis tool
Keywords
formal specification; high level synthesis; network synthesis; temporal logic; automated synthesis tool; circuit definition; digital circuits; formally based circuit synthesis; high level behavioural specification; interval temporal logic; Aerospace electronics; Automata; Circuit synthesis; Digital circuits; Hardware design languages; Information systems; Logic circuits; Logic programming; Software systems; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
EUROMICRO 94. System Architecture and Integration. Proceedings of the 20th EUROMICRO Conference.
Conference_Location
Liverpool
Print_ISBN
0-8186-6430-4
Type
conf
DOI
10.1109/EURMIC.1994.390402
Filename
390402
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