• DocumentCode
    2590917
  • Title

    Design and test of decision feedback equalizers for 80 Gbit/s Bit rate and beyond

  • Author

    Awny, A.S. ; Thiede, A. ; Scheytt, J.

  • Author_Institution
    University of Paderborn, Germany
  • fYear
    2011
  • fDate
    5-10 June 2011
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Summary form only given, as follows. Modification of the 1-tap parallel look-ahead decision feedback equalizer (DFE) architecture is developed using Boolean algebra to enable its operation at 80Gbps and beyond. Measurement techniques which can be generally applied to the testing of this as well as to other DFE architectures are devised. The equalizer´s wide band clock distribution network enables its operation from 25 to 80Gbps. The equalizer is designed in a 0.13um SiGe:C BiCMOS technology, dissipates 4W and occupies 2mm2
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International
  • Conference_Location
    Baltimore, MD
  • ISSN
    0149-645X
  • Print_ISBN
    978-1-61284-754-2
  • Electronic_ISBN
    0149-645X
  • Type

    conf

  • DOI
    10.1109/MWSYM.2011.5973129
  • Filename
    5973129
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2590917