An RCC receiver IC with TAD-DQD and ADPLL using frequency multiplying number with decimals

A 0.18-mum CMOS RCC (radio-controlled clock) receiver IC with TAD (Time A/D converter) and ADPLL was realized. This IC, which receives low-frequency (LF) standard time waves, performs AM detection with digital circuits. It has two key components. First, TAD is an all-digital analog-to-digital converter, whose voltage resolution is settable (15 muV/LSB at 100 kS/s and 3.1 mV/LSB at 20 MS/s). Second, the ADPLL applying a frequency multiplying number of 4.8828125 generates a 160 kHz ADC (TAD) sampling clock from a 32.768 kHz quartz-clock for digital detection processing. The DSP section, which operates as an adder-subtractor and digital filters, consists of standard cells (75,000 gates). This test IC achieved minimum detectable sensitivity of 0.7 muVrms and maximum detectable sensitivity of 100 mVrms for a standard time wave of 40 kHz at the LNA input terminal. Since the TAD sampling frequencies are settable with desirable multiplying numbers with decimals, the IC can receive different kinds of LF standard time waves such as 40 kHz (JP), 60 kHz (JP), 77.5 kHz (DE), and 68.5 kHz (CN) without any use of quartz-crystal filters.