Simplified forced convergence decoding algorithm for low power LDPC decoders

Author

Byung Jun Choi ; Myung Hoon Sunwoo

Author_Institution

Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea

fYear

2014

fDate

17-20 Nov. 2014

Firstpage

663

Lastpage

666

Abstract

This paper proposes a simplified forced-convergence (SFC) algorithm to reduce the computational complexity for low-density parity-check (LDPC) decoding. To reduce the computational complexity, the proposed algorithm uses the modified check node (CN) operation that does not use a condition for deactivating CNs. Therefore, the proposed SFC algorithm uses only one threshold value while the existing forced-convergence (FC) algorithm uses two threshold values. The simulation results show that SFC achieves a bit error rate (BER) performance close to min-sum (MS) algorithm. SFC can reduce the computational complexity of check node by approximately 22.21% compared to FC.

Keywords

codecs; convergence; decoding; error statistics; low-power electronics; parity check codes; BER; CN operation; LDPC decoding; MS algorithm; SFC algorithm; bit error rate; check node operation; computational complexity; low power LDPC decoders; low-density parity-check decoding; min-sum algorithm; simplified forced convergence decoding algorithm; Bit error rate; Computational complexity; Iterative decoding; Manganese; TV; belief-propagation decoding algorithm; forced-convergence; low-density parity-check codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on

Conference_Location

Ishigaki

Type

conf

DOI

10.1109/APCCAS.2014.7032868

Filename

7032868