Title :
Process roadmap and challenges for metal barriers [copper interconnects]
Author :
Moon, P. ; Dubin, V. ; Johnston, S. ; Leu, J. ; Raol, K. ; Wu, C.
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
Copper interconnects require two types of barrier layers: a liner on the sides and bottoms of the damascene features and a cap on top of the damascene features. The key functions of the barrier layers are to prevent copper and oxygen diffusion and promote adhesion with both the interlayer dielectric (ILD) and the copper. The cap layer must also protect the copper from corrosion during subsequent patterning steps and act as an etchstop for partially landed vias. Most copper damascene processes use a PVD Ta and/or Ta(N) alloy liner and PECVD SiN or SiCN dielectric cap. However, as copper interconnects continue to scale to finer dimensions these metal barrier technologies become problematic due to wiring resistance and current density issues. This paper describes some of the alternative liner and cap technologies that are being developed to address these issues.
Keywords :
adhesion; chemical vapour deposition; copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; silicon compounds; tantalum; tantalum compounds; Cu; PECVD; PVD; SiCN; SiN; Ta; TaN; adhesion; cap layer; copper diffusion; copper interconnects; corrosion protection; current density; damascene features; dielectric cap; etchstop; interconnect liner; interlayer dielectric; metal barrier layers; oxygen diffusion; partially landed vias; patterning; wiring resistance; Adhesives; Atherosclerosis; Copper alloys; Corrosion; Dielectrics; Etching; LAN interconnection; Protection; Silicon compounds; Wiring;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269410