VLSI design of an interference canceller for QPSK OFDM-IDMA systems

With growing demand of machine to machine (M2M) communication, wireless communication systems request simultaneous connections for many terminals to cope with thus increasing communication throughput. We focus on interleave division multiple access (EDMA) that has superior user detection performance and describe a VLSI design of an interference canceller that performs user detection in QPSK OFDM-IDMA systems. A conventional interference canceller has an issue of degradation in interleave memory throughput. We propose a new architecture of dual-frame processing in an interference canceller by making use of an OFDM-DDMA frame structure. In FPGA implementation, the proposed architecture has shown fewer hardware resources compared with the conventional architecture.