An adaptive method for system level partitioning

Author

Wang, Tao ; Haggard, Roger L.

Author_Institution

Dept. of Electr. Eng., Tennessee Technol. Univ., Cookeville, TN, USA

fYear

1995

fDate

12-14 Mar 1995

Firstpage

375

Lastpage

378

Abstract

This paper presents a novel adaptive-weight system level partitioning algorithm. The algorithm helps designers to achieve optimal performance in the early stage of high level synthesis. It subdivides a VHDL behavioral description into sub-descriptions that will fit a multi-chip implementation. By adaptively adjusting its cost function, the method can automatically search for the best performance under given physical constraints. The paper also provides examples to demonstrate the effectiveness of the algorithm

Keywords

circuit optimisation; hardware description languages; high level synthesis; logic partitioning; multichip modules; VHDL behavioral description; adaptive-weight system level partitioning algorithm; cost function; high level synthesis; multi-chip implementation; optimal performance; Adaptive systems; Algorithm design and analysis; Clustering algorithms; Constraint optimization; Cost function; Design optimization; High level synthesis; Iterative algorithms; Iterative methods; Partitioning algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory, 1995., Proceedings of the Twenty-Seventh Southeastern Symposium on

Conference_Location

Starkville, MS

ISSN

0094-2898

Print_ISBN

0-8186-6985-3

Type

conf

DOI

10.1109/SSST.1995.390523

Filename

390523