A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design

Researches show that the bulk of the power consumption of a processor system goes to the cache memory of the processor. Cache sub-banking and block buffering are the two most common techniques in reducing the power consumption of the cache memory. However, these techniques have only been applied to a single processor. This research study introduces these two techniques to multiprocessor systems. Parallel execution will be the biggest issue that will affect the behavior of the cache sub-banking and block buffering technique. Previous research claimed that the execution of a program spread between more than one processor tends to decrease its locality of reference compared to the same program executing on one processor which will also be studied. This research work created RTL models of cache architectures that implements the cache sub-banking and the block buffering technique. Memory traces were gathered from the M5 simulator which will serve as the stimulus and test bench for the RTL models. The data results showed that inserting a block buffer between level one cache and level two cache in a multiprocessor environment will prove useless because the size of the block buffer will never be enough to sustain the demands of the level one cache. The setup with 1024 set and 8 way which uses 1MB of cache memory is the best architecture to use for a cache architecture with cache sub-banking technique. It produce a miss rate of 12.31% which is an average miss rates from 16 different test bench.