A synthesizable IP core for DVB-S2 LDPC code decoding

Author

Kienle, Frank ; Brack, Torben ; Wehn, Norbert

Author_Institution

Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany

fYear

2005

fDate

7-11 March 2005

Firstpage

100

Abstract

The new standard for digital video broadcast DVB-S2 features low-density parity-check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative process. For DVB-S2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255 Mbit/s for base station applications. In this paper we show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0.13 μm CMOS technology.

Keywords

CMOS integrated circuits; channel coding; digital signal processing chips; digital video broadcasting; industrial property; iterative decoding; parity check codes; television standards; 0.13 micron; 255 Mbit/s; CMOS technology; DVB-S2 standard; LDPC code; ST Microelectronics; base station applications; channel coding; digital video broadcast; iterative decoding; low-density parity-check codes; synthesizable IP core; Base stations; CMOS technology; Channel coding; Code standards; Data processing; Digital video broadcasting; Hardware; Iterative decoding; Parity check codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2005. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2288-2

Type

conf

DOI

10.1109/DATE.2005.39

Filename

1395802