Impact of lithography overlay on 0.8 micron CMOS layout design rules

This article describes an impact of lithography overlay accuracy on 0.8 micron CMOS design rules. The trial design rules for test circuits based on large tolerance of 0.8 micron technology. Fabricated test circuits showing the overlay accuracy, between polysilicon and active layers, are 0.27 micron in X-direction and 0.25 micron in Y-direction. This is acceptable compared with the 0.4 micron value from design rule. The other design rule, contact to polysilicon layers, is also acceptable because the accuracy in X and Y directions are 0.13 and 0.08 micron, respectively. These are smaller than the design rule tolerance at 1.0 micron. Even though the total overlay value from test circuits is lower than the trial design rules, the current fabrication technology at TMEC still employs the trial design rules with higher tolerance values. Since tighter design rules will complicate the fabrication process in other modules. Furthermore, the existing rules still perform well enough for the devices being fabricated at TMEC, because they are not overly complex or requiring dense transistor packing.