• DocumentCode
    2597044
  • Title

    Performance evaluation of multi-core intel xeon processors on basic linear algebra subprograms

  • Author

    Soliman, Mostafa I.

  • Author_Institution
    Electr. Eng. Dept., South Valley Univ., Aswan
  • fYear
    2008
  • fDate
    25-27 Nov. 2008
  • Firstpage
    3
  • Lastpage
    9
  • Abstract
    Multi-core technology is a natural next step in delivering the benefits of Moore´s law to computing platforms. On multi-core processors, the performance of many applications would be improved by parallel processing threads of codes using multi-threading techniques. This paper evaluates the performance of the multi-core Intel Xeon processors on the widely used basic linear algebra subprograms (BLAS). On two dual-core Intel Xeon processors with hyper-threading (HT) technology, our results show that a performance of around 20 GFLOPS is achieved on Level-3 (matrix-matrix operations) BLAS using multi-threading, SIMD, matrix blocking, and loop unrolling techniques. However, on a small size of Level-2 (matrix-vector operations) and Level-1 (vector operations) BLAS, the use of multi-threading technique speeds down the execution because of the thread creation overheads. Thus the use of Intel SIMD instruction set is the way to improve the performance of single-threaded Level-2 (6 GFLOPS) and level-1 BLAS (3 GFLOPS). When the problem size becomes large (cannot fit in L2 cache), the performance of the four Xeon cores with HT is less than 2 and 1 GFLOPS on Level-2 and level-1 BLAS, respectively, even though eight threads are executed in parallel.
  • Keywords
    mathematics computing; matrix algebra; multi-threading; performance evaluation; Intel SIMD instruction set; Moore law; basic linear algebra subprogram; hyper-threading technology; loop unrolling technique; matrix blocking; matrix-matrix operation; matrix-vector operation; multicore Intel Xeon processor; multithreading technique; parallel processing thread; performance evaluation; Clocks; Hardware; Linear algebra; Moore´s Law; Multicore processing; Pipelines; Registers; Software maintenance; Vectors; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Engineering & Systems, 2008. ICCES 2008. International Conference on
  • Conference_Location
    Cairo
  • Print_ISBN
    978-1-4244-2115-2
  • Electronic_ISBN
    978-1-4244-2116-9
  • Type

    conf

  • DOI
    10.1109/ICCES.2008.4772956
  • Filename
    4772956