Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

Author

Skordas, Spyridon ; Tulipe, D.C.L. ; Winstel, Kevin ; Vo, T.A. ; Priyadarshini, Deepika ; Upham, A. ; Song, Dong ; Hubbard, Alex ; Johnson, R. ; Cauffman, Kristian ; Kanakasabapathy, S. ; Lin, Weisi ; Knupp, Seth ; Malley, M. ; Farooq, M.G. ; Hannon, R. ;

Author_Institution

Semicond. R&D Center, IBM Corp., Albany, NY, USA

fYear

2012

fDate

22-23 May 2012

Firstpage

203

Lastpage

208

Abstract

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

Keywords

etching; three-dimensional integrated circuits; wafer bonding; 3D systems integration; Si; TSV-last 3D integration strategy; TSV-last integration; electrical open/short yield learning; mechanical/wet etch assisted wafer thinning; oxide fusion wafer bonding; size 300 mm; through-wafer electrical TSV test chains; wafer thinning development; wafer-scale oxide fusion bonding; 3D integration; TSV; through-silicon via; wafer bonding; wafer thinning;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Temperature Bonding for 3D Integration (LTB-3D), 2012 3rd IEEE International Workshop on

Conference_Location

Tokyo

Print_ISBN

978-1-4673-0743-7

Type

conf

DOI

10.1109/LTB-3D.2012.6238091

Filename

6238091