Title :
Test structure for evaluation of 1/f noise in CMOS technologies
Author :
Chang, Z.Y. ; Sansen, W.
Author_Institution :
Dept. of Electrotech., Catholic Univ. of Leuven, Heverlee, Belgium
Abstract :
A new test structure for evaluation of 1/f noise in CMOS technology is presented. The structure consists of both n-type and p-type MOS transistors with various geometrical dimensions. By direct measurements of the spectrum of drain current fluctuations of MOS transistors in the test structure, the dependences of 1/f noise on the transistor dimensions and bias conditions can be determined. From the measurement results the 1/f noise factor KF can be calculated.
Keywords :
CMOS integrated circuits; current fluctuations; electron device noise; insulated gate field effect transistors; integrated circuit testing; random noise; 1/f noise; CMOS technologies; bias conditions; drain current fluctuations; geometrical dimensions; n-type MOST; noise factor; p-type MOS transistors; test structure; transistor dimensions; CMOS technology; Current measurement; Integrated circuit noise; Low-frequency noise; MOSFET circuits; Noise level; Noise measurement; Operational amplifiers; Radio frequency; System testing;
Conference_Titel :
Microelectronic Test Structures, 1989. ICMTS 1989. Proceedings of the 1989 International Conference on
Print_ISBN :
0-87942-714-0
DOI :
10.1109/ICMTS.1989.39299
