Compact Models of Voltage Drops in Power Delivery Network for TSV-Based Three-Dimensional Integration

Author

Huanyu He ; Jian-Qiang Lu

Author_Institution

Dept. of Electr., Comput., & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA

Volume

34

Issue

3

fYear

2013

fDate

Mar-13

Firstpage

438

Lastpage

440

Abstract

This letter reports on compact models of voltage (IR) drops in a power delivery network (PDN) for through-silicon-via-based 3-D integration and packaging. The 3-D PDN is modeled with SPICE to investigate the dc voltage distribution in 3-D chip stacks. Analytical formulas are derived for estimating voltage drops for two typical types of vertical interconnect arrangements: uniform and peripheral distributions. With good agreements, analytical calculations reveal that the voltage drop has a quadratic correlation with the number of chips in a stack. The compact models provide important insights of 3-D PDNs for 3-D system design.

Keywords

SPICE; electric potential; integrated circuit packaging; three-dimensional integrated circuits; SPICE; TSV-based three-dimensional integration; packaging; power delivery network; through-silicon-via; voltage drops; Integrated circuit modeling; Packaging; Power grids; Solid modeling; Through-silicon vias; 3-D integration; $IR$ drop; modeling; packaging; power delivery network (PDN); through-silicon via (TSV);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2013.2238214

Filename

6419754