Low-power driven technology mapping under timing constraints

Most research in logic synthesis has mainly focussed on area and delay optimizations. In this paper, we focus on the problem of mapping a technology independent circuit to a library of gates such that power is minimized while satisfying some user-specific timing constraints. Such timing constraints can often be rather stringent. We present a new technology mapping algorithm based on extending the dynamic programming paradigm for low-power under timing constraints. The effectiveness of this algorithm is based on two key observations: first, the switching activities of different nodes in a network can vary significantly; and second, the power contribution from a node is directly proportional to its switching activity. Therefore, it is possible to significantly optimize for low power by minimizing the fanout load of “high” switching nodes whenever possible, and trying to compensate instead for delay at the fanout of “lower” switching nodes. In addition to extending dynamic programming for low power under timing constraints, we have also developed optimization techniques that can be used to optimize further for low power and delay. We present experimental results on a large set of standard benchmarks to demonstrate that substantial optimization is possible