A hybrid router combining circuit switching and packet switching with bus architecture for on-chip networks

Since applications can generate both streaming and best effort traffics, there is then a need for an on-chip network to provide QoS for streaming traffic and to guarantee packets delivery without loss for best effort traffic. Instead of handling both streaming and best-effort traffic in a circuit or packet switched network, which often leads to a complex design, we propose a hybrid router combining circuit and packet switching with bus architecture. It efficiently and separately handles streaming and best effort traffics. Code Division Multiple Access “CDMA” is used in circuit switching and bus to improve resources utilization. The proposed router architecture has been synthesized in both ASIC 65 nm and FPGA. Synthesis results show that a practical network on chip can be built using the proposed router architecture.