Design and realization of intermediate down-sampling for SAR based on FPGA

Under the condition of meeting resolution, the SAR real-time image can satisfy the demands of the processing band by pre-filter and down-sample. Due to being in a special position in the signal processor, the ranger pre-filter needs very high operating speed and quick frequency response. The pre-filter principles and the methods are analyzed in this paper and the study is focused on the realization of range down-sampling using FPGA. This paper pay more attention to the range down-sampling which following the digital orthogonal mixing. After analyzing the polyphase arithmetic, a new method of down-sampling which is implemented in FPGA is put forward in this paper. Validated by simulation, circuit operates reliability and fulfils design demand.