DocumentCode
2601751
Title
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
fYear
1996
fDate
6-8 Nov. 1996
Firstpage
2
Abstract
The following topics were dealt with: defect avoidance; yield prediction; reliability enhancement; layout driven test; process data analysis; fault diagnosis; fault tolerant structures; circuit synthesis; and fault-tolerance approaches
Keywords
VLSI; built-in self test; circuit CAD; fault diagnosis; fault tolerant computing; integrated circuit design; integrated circuit reliability; integrated circuit testing; integrated circuit yield; logic CAD; network routing; circuit synthesis; defect avoidance; fault diagnosis; fault tolerant structures; layout driven test; process data analysis; reliability enhancement; self-checking designs; yield prediction;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location
Boston, MA, USA
ISSN
1550-5774
Print_ISBN
0-8186-7545-4
Type
conf
DOI
10.1109/DFTVS.1996.571979
Filename
571979
Link To Document