A Novel Low Leakage-Current Ni SALICIDE Process in nMOSFETs on Si(110) Substrate

Author

Yamaguchi, T. ; Kashihara, K. ; Kudo, S. ; Hayashi, K. ; Hashikawa, N. ; Okudaira, T. ; Tsutsumi, T. ; Maekawa, K. ; Oda, H. ; Asai, K. ; Kojima, M.

Author_Institution

Renesas Technol. Corp., Hyogo

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

139

Lastpage

142

Abstract

A novel low leakage-current Ni SALICIDE process in nMOSFETs on Si(110) is proposed. It is found for the first time that the anomalous off-state leakage-current (I_off) in nMOSFETs on Si(110) is caused due to the inherent Ni silicide encroachment toward the channel region. Especially, <110> channel on Si(110) has fatal defect for CMOS fabrication. We propose two methods to suppress the anomalous I_off, the creative ingenuity of design layout within SRAM and Si ion implantation (Si I.I.) technique. These two methods are quite effective to realize high performance and low cost CMOS devices on Si(110).

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; leakage currents; nickel compounds; silicon; CMOS devices; CMOS fabrication; Ni SALICIDE process; SRAM; Si; Si ion implantation technique; nMOSFET; off-state leakage-current; Degradation; Electron mobility; Fabrication; Ion implantation; MOS devices; MOSFETs; Semiconductor films; Silicides; Stacking; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418884

Filename

4418884