Title :
Interconnect transient simulation in the presence of layout and routing uncertainty
Author :
Rong, Aosheng ; Cangellaris, Andreas C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois, Urbana, IL, USA
Abstract :
A methodology is presented for the calculation of the transient transmission-line response of package-level or board level interconnects in the presence of layout and routing uncertainty. The proposed methodology makes use of the generalized polynomial chaos framework and advances in sparse stochastic collocation for interpolation and sampling in the probability space defined by the random variables that describe routing un certainty. In this manner, a modeling framework is established that facilitates the computation of the statistics of the transient response and its post-processing for the purpose of assessing the impact of interconnect layout and routing uncertainty on signal distortion and crosstalk.
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; interpolation; board level interconnects; interconnect transient simulation; layout uncertainty; package level; polynomial chaos framework; probability space; random variables; routing uncertainty; sparse stochastic collocation; transient transmission line response; Chaos; Layout; Polynomials; Random variables; Routing; Stochastic processes; Uncertainty; interconnects; signal integrity; stochastic modeling;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-9398-2
Electronic_ISBN :
pending
DOI :
10.1109/EPEPS.2011.6100214